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Low-power CMOS research

The ACMOS group at USC's Information Sciences Institute is exploring new ways to build low-power CMOS electronic circuits. In contrast to the more common approaches to reduce power dissipation, our circuits recycle the circuit energies rather than dissipate them as heat. (This is what the recycling symbol in the logo alludes to.) The ACMOS group has been active in this research area since 1992.

We focus on the dynamic dissipation, which typically dominates the power dissipation in CMOS switching circuits. This dissipation is caused by repetitive charging and discharging of capacitive loads. Our techniques allow a designer to trade transition time for dissipation, without changing the voltage swing or the capacitive load. In contrast, most other low-power CMOS circuit techniques involve reduction of the voltage swing.

With our techniques, fCV2 is not the lower limit to the dynamic dissipation. This property sets our circuits apart from those using other low-power techniques.

We have converged on two broad classes of circuits and techniques which we are investigating further. Stepwise charging appears to be the most immediately applicable of these. Our most recent application of this technique is an output pad driver with a transition time of 10 ns and a dissipation of less than 70% of fCV2.

Resonant charging is our second area of emphasis. We have built and tested several small logic circuits based on these ideas. We are presently designing a 16-bit microprocessor which uses resonant charging throughout. We expect to be able to recycle 60%-75% of the energy used by the processor.

Our techniques can be applied in all cases where most of the dissipation is due to charging and discharging capacitive loads. This includes the gate and parasitic capacitances of CMOS chips, but also applications such as LCD panels and MEMS electrostatic actuators.

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