AC-1 Microprocessor

• Principal architect: Dr. Nestoras Tzartzanis, PhD
• Design Team: Nestoras Tzartzanis, Peiqing Wang, Huimin "Deadman" Li, XingYu Jiang, Johnny Svensson, and Bill Athas
• Resonant charging for low power
• Clock-powered logic
• On-chip dual resonators with off-chip inductors, US Patent #5,559,478
• Cn-chip conventional clock driver (used for comparison purposes)
• 16-bit datapath and 16-bit instruction set
• Dynamic (precharged) mostly-nMOS circuit logic
• 13,000 transistors
• Custom layout using Magic
• 0.5um nwell bulk CMOS (0.8um part shown)
• 58.8MHz top speed (laboratory measurement)
• 21mW at 74MHz from PowerMill simulation
• For more information, please see our publications

MD-1 Microprocessor

• Principal designer: Dr. Weihua Mao, PhD
• Design Team: Weihua Mao, Weichuan Liu, Johnny Svensson, Rajat Lal, Lena Petersson, Rajat Lal, and Bill Athas
• Custom designed for MicroDisplay Corporation for use as an integrated graphics processor
• Resonant charging for low power
• Advanced clock-powered logic
• On-chip dual resonators with off-chip inductors, US Patent #5,559,478
• 16-bit datapath and 16-bit instruction set
• Special-purpose MDX (Misha Display eXtension) instructions for pixel operations
• Static CMOS logic.
• Synthesized from standard and custom cells using Duet Epoch toolset
• 0.5um nwell bulk CMOS (HP14B)
• < 2mW @ 14.5MHz (Vdd=1.7V), laboratory measurement

Energy-Recovery RAM

• Principal designer: Dr. Nestoras Tzartzanis, PhD
• Designers: Nestoras Tzartzanis, Johnny Svensson, and Bill Athas
• Resonant charging for low power
• Advanced, low-swing, clock-powered logic
• On-chip dual resonators with off-chip inductors, US Patent #5,559,478
• Custom layout using Magic
• Current-mode sense amps
• 0.5um nwell bulk CMOS (HP14B)

DC2.00 Microprocessor

• Designers: Weihua Mao, Apoorv Srivastava, Jay Moon, Kisup Chong, and Bill Athas
• Conventional low-power logic
• Single-phase clock
• 5-stage pipeline
• 32-bit datapath
• 16-bit instructions simulation.
• 200 MHz Low-power, high-speed postcharged register file
• 200 MHz parallel-prefix 32-bit adder
• 129mW at 133MHz from PowerMill
• Synthesized from standard and custom cells using Duet Epoch toolset
• 0.5um nwell bulk CMOS (HP14B)

LCD Microdisplay

• Principal designer: Rajat Kumar Lal
• Designers: Rajat Lal, Johnny Svensson, and Bill Athas
• 120 x 160 pixel display
• 5 volt operation
• Stepwise charging for low power, US Patent #5,473,526
• 55% total energy savings compared to ideal conventional display
• Synthesized from standard and custom cells using Duet Epoch toolset
• 0.5um nwell bulk CMOS (HP14B)

Stepwise pad driver

• Principal designer: Johnny Svensson
• Designers: Johnny Svensson, ChenHua Wang, and Bill Athas
• 5V, 50mA pad driver for 100pF loads
• 20% energy savings for 10ns transition times
• sub-3ns versions also avialable for smaller loads
• Custom Magic layout

AC-1 SOI Clock-Powered Microprocessor

• Principal conversion artist: Dr. Nestoras Tzartzanis, PhD
• Resonant charging for low power
• Clock-powered logic
• On-chip dual resonators with off-chip inductors, US Patent #5,559,478
• 16-bit datapath and 16-bit instruction set
• Dynamic (precharged) mostly-nMOS circuit logic
• 13,000 transistors
• Custom layout using Magic
• 0.25um Lincoln Labs Silicon on Insulator (SOI) CMOS
• 28mw at 73.4 MHz top speed (laboratory measurement)
• For more information, please see our publications