A Resonant Signal Driver For Two-Phase, Almost-Non-Overlapping Clocks
W.C. Athas, L."J." Svensson, and N. Tzartzanis
University of Southern California - Information Sciences Institute
Marina del Rey, California 90292-6695
Abstract
We describe a driver circuit for reducing
the power dissipated when driving heavily loaded
signals such as the clock lines of a VLSI chip.
The design exhibits good power efficiency
across a wide range of frequencies.
We have tested the driver with a prototype
shift-register chip which had a clock line
load in the hundreds of picofarads.
The worst-case overall dissipation was 35% of
fCV2
at 13MHz and 5V.