Design and Analysis of a Low-Power Energy-Recovery Adder
Nestoras Tzartzanis and William C. Athas
University of Southern California - Information Sciences Institute
Marina del Rey, California 90292-6695
Abstract
In this paper, an 8-bit energy-recovery adder design is
evaluated through SPICE simulation for energy dissipation
and delay time, and is compared against
a supply-voltage-scaled adder. The experimental results
indicate that the energy-recovery adder outperforms
the supply-scaled version for a wide range of frequencies.