Reversible Logic Issues in Adiabatic CMOS

Abstract

Power dissipation in CMOS circuits has become increasingly important for the design of portable, embedded, and high-performance computing systems. Our VLSI research group at the USC Information Sciences Institute has investigated a novel form of energy conserving logic suitable for CMOS. Through small chip-building experiments, we have demonstrated the low-power operation of simple logic functions. These chips have used logical reversibility on a small, sometimes trivial, scale to achieve their low-power operation. In moving towards more complex functions, the role of reversibility will increase. This paper addresses two problem areas that we have found to be crucial to successfully realizing low-power operation of CMOS chips using reversible logic techniques. The first area is the energy-efficient design of the combined power supply and clock generator. The second is the logical overhead needed to support reversible logic functions. The first problem area, though formidable, seems amenable to systematic approaches. Significant inroads have been made towards finding practical, efficient solutions. The second, however, appears to be by far the more difficult hurdle to overcome if reversible logic is to become an attractive approach for reducing power dissipation in CMOS.